The present invention relates to an input buffer used in a semiconductor memory device and more particularly to an input buffer capable of operating at a high speed by using a BiCMOS (bi-complementary metal oxide semiconductor) circuit.
Generally, input buffers in semiconductor memory devices, which convert a transistor-transistor logic (TTL) signal received from the exteriors of a chip to a CMOS logic signal, are installed in every input terminal within the chip that receives a plurality of external input signals. One of the problems associated with conventional input buffers is variations variation of an input trip level due to external factors, for example, power supply voltage variation, process condition, and temperature variation, etc. The variation in the input trip level makes the operation speed of the input buffer undesirably low and, more particularly, reduces overall operational speed of BiCMOS memory devices for which high speed operation is desired, for example, BiCMOS static random access memory devices. Further, when the semiconductor memory device is in a stand-by state due to a slight voltage swing of TTL input level, unnecessary power consumption can occur. However, this power consumption problem has been solved by using the input of an inverter positioned in the input side as an activating signal.
FIG. 1 is a circuit diagram illustrating a conventional input buffer using a BiCMOS circuit, which is similar to circuit diagrams of U.S. Pat. Nos. 5,047,670 and 5,225,717. A typical input buffer contains two inverters with serial stages, the input buffer of FIG. 1 includes a first stage inverter 10 and a second stage inverter 20. In the first stage inverter 10, a p-channel insulated gate field effect transistor IGFET (hereinafter referred to as p-channel transistor) MPR having a gate connected to substrate potential (or a ground potential) Vss serves to supply a current flowing from the power supply voltage Vcc to a source of p-channel transistor MPS having a gate connected to an external input signal XS. The p-channel transistor MPS and n-channel transistor MNS gated by the external input signal XS have different channel sizes from each other. The external input signal XS substantially has a voltage swing width between 0-3V, while a node 112 (which has a potential in accordance with the gating state of the p-channel transistor MPS and the n-channel transistor MNS, being connected to a base of an npn bipolar transistor Q1) has a voltage swing width between Vcc-0V. The p-channel transistor MPS is susceptible to variation of the power supply voltage, due to its physical characteristic. As a result, the channel width of the p-channel transistor MPS is designed to be smaller than that of the n-channel transistor MNS.
If the external input signal XS is changed from a logic "high" state to a logic "low" state, the p-channel transistor MPS is turned on and the potential in node 112 is at a power supply voltage Vcc level. Thereby, the npn bipolar transistor Q1 is turned on and potential in node 113 of the first stage inverter 10 is at the logic "high" state. If an output signal of the first stage inverter 10 being at the logic "high" state is applied to a gate of n-channel transistor MN1, an npn pull-down bipolar transistor Q3 in the second stage inverter 20 is turned on and an internal signal S is generated in the "low" state. At this time, since a signal being in the logic "low" state is applied to a base of npn pull-up bipolar transistor Q2 using an inverter comprised of a p-channel transistor MP1 and an n-channel transistor MN3, the npn pull-up bipolar transistor Q2 is in a turn-off state. Also, the output signal in the logic "High" state from the first stage inverter 10 is changed to the logic "high" "low" state of an inverter comprised of a p-channel transistor MP2 and an n-channel transistor MN4, and then, respectively applied to an inverter comprised of a p-channel transistor MP3 and an n-channel transistor MN5, and to a gate of an n-channel transistor MN6. Then, since a signal in the logic "high" state is applied to a base of an npn pull-up bipolar transistor Q4, the npn pull-up bipolar transistor Q4 is turned on and a negative phase internal signal SB being in the logic "high" state is generated. At this time, an npn pull-down bipolar transistor Q5 is turned off by the n-channel transistor MN6 being turned off and n-channel transistor MN7 being turned on.
In operation of the conventional input buffer of FIG. 1, a response state in the node 112 to the external input signal XS is changed due to variation of the power supply voltage Vcc level. FIG. 2 is a graph illustrating voltage waveforms in node 112 responsive to the external input signal XS being swung in the voltage between 0V to 3V. The waveform V112x shows a voltage waveform in node 112 responsive to the external input signal XS under the condition (hereinafter referred to as a first condition) of a power supply voltage of 4.2 V and a temperature of 100.degree. C. And the waveform V112y shows a voltage waveform in the node 112 responsive to the external input signal XS under the condition (hereinafter referred to as a second condition) of a power supply voltage of 5.8 V and a temperature of 100.degree. C. In case where the external input signal XS is changed from the logic "high" state to the logic "low" state, if the power supply voltage Vcc is increased, a voltage in the source of the p-channel transistor MPS of FIG. 1 is accordingly increased. As a result, a voltage value .vertline.V.sub.GS .vertline. between the gate and the source of the p-channel transistor MPS is high. Thereby, under the second condition, the potential in the node 112 is in the logic "high" state in potential of 1.6 V before the potential of the external input signal XS falls below 1.5 V. In the first condition, the potential in the node 112 is in the logic "high" state in potential of 1.3 V after the potential of the external input signal XS falls below 1.5 V. As a result, from the waveforms with different power supply voltage Vcc level from each other, it can be appreciated that an intermediate transition voltage level difference .increment.VIN in the node 112 (if the logic "high" state is considered as 2.4 V) is approximately 0.3 V.
In case of rising of the power supply voltage (for example. Vcc=5.8 V), the existence of the intermediate transition voltage level difference .increment.VIN of 0.3 V enables an input low voltage VIL to be relatively quickly generated in the node 112, and contrarily, in case of falling of the power supply voltage (for example, in case of the first condition), generation of the input low voltage VIL in the node 112 takes considerable. Similarly, when the external input signal XS is changed from the logic "low" state to the logic "high" state, in case of a rising of the power supply voltage, an input high voltage VIH takes considerable time to generate, while, in case of falling of a the power supply voltage, the input high voltage VIH is relatively quickly generated. Such variation of the input high voltage VIH and the input low voltage VIL results in unstable CMOS logic operation in the semiconductor memory device by as much as that of the power supply voltage.
Moreover, in case of rising of a the power supply voltage, the p-channel transistor MPS is designed to have a small channel width compared to the n-channel transistor MNS, in order to adjust the voltage swing widths of the external input signal XS and in the node 112 Accordingly p-channel transistor MPS has a weak current driving capability, and it is understood it takes for the duration that the node 112 to changed to the logic "high" state in response to the external input signal XS is inevitably delayed. Since such an inevitable delay duration is required for all of the external input signals applied to the chip, as shown in the input buffer of FIG. 1, this results in operational speed delays in the semiconductor memory device. For instance, if the external input signal XS is an address signal, time t.sub.AA indicative of the period taken from the input of the address signal and the output of data is delayed and in consistently varied due to variation of the power supply voltage level.